The present invention relates to a serial-parallel converter circuit for converting serial data which have been inputted time-sequentially into parallel data, and more particularly to a serial-parallel converter circuit capable of relaxing a timing-restriction in high speed operation.
A conventional serial-parallel converter circuit is disclosed in Japanese laid-open patent publication No. 4-38017. FIG. 1 is a diagram illustrative of the conventional serial-parallel converter circuit. The conventional serial-parallel converter circuit comprises a shift resistor 10 for generating latch timing, a flip-flop group 12 of flip-flop circuits 121, 122, 123 and 124, a transit resistor 14, and an output-stage resistor 16. The shift resistor 10 receives a clock signal CLK and a signal LOAD, so that the conventional serial-parallel converter circuit converts the serial data DIN into parallel data D01, D02, D03 and D04 which have plural bits.
The shift resistor 10 for generating the latch timing is connected to an OR-gate 18. The shift resistor 10 receives a clock signal CLK and a signal LOAD, so that the shift resistor 10 outputs four latch signals L1, L2, L3 and L4 in pulse form which are different in phase by one-cycle of the clock. The number of the outputted latch signals L1, L2, L3 and L4 corresponds to the number of the bits of the parallel data or four bits.
The flip-flop group 12 comprises the four flip-flip circuits 121, 122, 123, and 124 which are connected to the shift resistor 10, so that the first flip-flop 121 receives the first latch signal Li, the second flip-flop 122 receives the second latch signal L2, the third flip-flop 123 receives the third latch signal L3, and the fourth flip-flop 124 receives the fourth latch signal L4. Each of the four flip-flip circuits 121, 122, 123, and 124 receives a time-sequential input of the serial data DIN, so that each of the four flip-flip circuits 121, 122, 123, and 124 latches the serial data DIN on the basis of the latch signal L1, L2, L3 or L4 as the clock.
The transit resistor 14 is connected to the first and second flip-flops 121 and 122 for receiving output data DT01 and DT02 from the first and second flip-flops 121 and 122 respectively, so that the transit resistor 14 latches the output data DT01 and DT02. The transit resistor 14 is also connected to the shift resistor 10 for receiving the third latch signal L3 from the shift resistor 10, so that the transit resistor 14 latches the output data DT01 and DT02 on the basis of the third latch signal L3 as a clock.
The output stage resistor 16 is connected to the transit resistor 14 for receiving output data DT11 and DT12 from the transit resistor 14. The output stage resistor 16 is connected to the third and fourth flip-flops 123 and 124 for receiving the third and fourth output data DT13 and DT14 from the third and fourth flip-flops 123 and 124 respectively. The output stage resistor 16 is also connected to the shift resistor 10 for receiving the second latch signal L2 from the shift resistor 10, so that the output stage resistor 16 performs to latch the output data DT11, DT12, DT13 and DT14 on the basis of the second latch signal L2 as a clock signal, whereby the output stage resistor 16 outputs parallel data D01, D02, D03 and D04.
FIG. 2 is a timing chart illustrative of waveforms of various signals of the conventional serial-parallel converter circuit of FIG. 1. During when serial data signals DIN are inputted into the flip-flop group 12 in synchronizing with the external clock signal CLK, the first to fourth latch signals L1, L2, L3 and L4 are transmitted from the shift resistor 10 to the flip-flop group 12 as clocks, so that the first to fourth output signals DT01, DT02, DT13, and DT14 are sequentially outputted from the first to fourth flip-flops 121, 122, 123 and 124 respectively.
Subsequently, the output signals DT01 and DT02 from the first and second flip flops 121 and 122 are transmitted to the transit resistor 14 and latched by the same on the basis of the third latch signal L3 as a clock, so that the first and second output signals DT11 and DT12 are outputted from the transit resistor 14.
The output signals DT11 and DT12 from the transit resistor 14 are transmitted to the output stage resistor 16. Further, the output signals DT13 and DT14 from the third and fourth flip-flops 123 and 124 are transmitted to the output stage resistor 16. The output signals DT11 and DT12 and the output signals DT13 and DT14 are latched by the output stage resistor 16 on the basis of the second latch signal L2 from the shift resistor 10, whereby parallel data D01, D02, D03, and D04 are outputted from the output stage resistor 16.
Only the shift resistor 10 is required to show the high speed operation. Other circuits such as the flip-flop group 12 are allowed to operate in the timing of 8-divided cycle of the input clock signals. The above conventional serial-parallel converter circuit is suitable for the high speed operations.
As can be understood from FIG. 2, the above conventional serial-parallel converter circuit has a disadvantage in that there is restricted a time until the second latch signal L2 is inputted into the output stage resistor 16 after the output data DT13 and DT14 are outputted from the transit resistor 14 and the output data are outputted from the third and fourth flip-flops 123 and 124. This time restriction means that a set-up time as a timing between input data and clock is restricted.
For example, only 2-divided cycle of the input clock CLK or a time period from t2 to t3 corresponds to the set-up time for the output stage resistor 16. The increase in frequency of the clock signals CLK in order to realize or improve the high speed performance shortens one cycle time of the clock signal CLK whereby the set-up time is also shortened. This makes it difficult to ensure a sufficient set-up time.
In the above circumstances, it had been required to develop a novel serial-parallel converter circuit free from the above problem.